Joonho Whangbo

[Github]

Hi! I'm a Ph.D. student in Computer Science at UC Berkeley, advised by krste asanović. I work mainly in computer architecture, focusing on simulation methodology, profiling, microarchitecture, and VLSI. Specifically, I'm interested in reducing perturbations during profiling, hardware based RTL emulation, intermediate representations for hardware, and microarchitecture.

Articles

• Developing a Frontend HDL
• Tips for Building an FPGA Shell
• Repurposing AI Chips for RTL Emulation
• How RTL Simulation Works
• XLS Considered Harmful
• Micro CAMS workshop 2024
• ASPLOS decompression 2024
• Is accelerator research really worth it?

Projects

• Processor based RTL emulation engine - documentation available here
• Hardware Description Language Embedded in Scala 3
• Simple RISC-V SuperScalar Out-of-Order Core (RV32I)
• Simulation driven full-stack system profiling
• RTL implementation of ZStd (de)compression accelerators
• Adding cross cacheline fetch support in BOOM
• Building better abstractions for hardware IRs
• Adding Multi-FPGA emulation support in FireSim (a.k.a FireAxe)
• Building a memory traffic generator to profile memory hierarchies of RISC-V SoCs
• Functional model of a block device

Potential Research Projects

• Undergrad (or early stage grad) research projects
• Using RISC-V Shadow Stack ISA Extensions for SW Profiling

Publications

• Joonho Whangbo, Edwin Lim, Chengyi Lux Zhang, Kevin Anderson, Abraham Gonzalez, Raghav Gupta, Nivedha Krishnakumar, Sagar Karandikar, Borivoje Nikolić, Yakun Sophia Shao, and Krste Asanović, "FireAxe: Partitioned FPGA-Accelerated Simulation of Large-Scale RTL Designs", To appear, In Proceedings of the 51th ACM/IEEE International Symposium on Computer Architecture (ISCA 2024), Buenos Aires, Argentina, June 2024. Paper PDF FireAxe

• Sagar Karandikar, Aniruddha N. Udipi, Junsun Choi, Joonho Whangbo, Jerry Zhao, Svilen Kanev, Edwin Lim, Jyrki Alakuijala, Vrishab Madduri, Yakun Sophia Shao, Borivoje Nikolić, Krste Asanović, and Parthasarathy Ranganathan, “CDPU: Co-designing Compression and Decompression Processing Units for Hyperscale Systems”, In Proceedings of the 50th ACM/IEEE International Symposium on Computer Architecture (ISCA 2023), Orlando, FL, USA, June 2023. Paper PDF, ACM DL (open-access) | CDPU

• Junseo Lee, Kwanseok Choi, Jungi Lee, Seokwon Lee, Joonho Whangbo, Jaewoong Sim, "NeuRex: A Case for Neural Rendering Acceleration", In Proceedings of the 50th ACM/IEEE International Symposium on Computer Architecture (ISCA 2023), Orlando, FL, USA, June 2023. Paper PDF, ACM DL (open-access) | NeuRex

Teaching

• While in Seoul National University

  • [430.315A: Digital Systems Design and Experiments]
  • [430.322: Computer Organization]

• While in UC Berkeley

  • [CS152/252: Computer Architecture]
  • [CS61C: Great Ideas in Computer Architecture]

Misc

Want to see a minimalistic Chisel example? Go checkout my Chisel-based priority queue! Chisel-Priority-Queue

• Tips for Building an FPGA Shell 2025-11-15
• ASPLOS 2024 Notes 2024-04-28
• Some research projects 2025-09-08
• Research on Domain Specific Architectures. Are they really worth it in academia? 2023-07-12
• Developing a Frontend HDL 2026-01-02
• Using Shadow Stacks to Reduce Performance Perturbation in Sampling Profilers 2025-09-15
• Repurposing AI Chips for RTL Emulation 2025-11-14
• XLS Considered Harmful 2024-08-24
• CAMs workshop 2024-11-03
• RTL Simulation 2025-05-07